发明名称 UNIVERSAL LOGIC CHIP
摘要 An integrated circuit or chip having a number of bond pads or inputs that may or may not have a bond wire connecting the pad to a supply voltage, ground or via a package pin to an external input when the chip is placed in the package. The circuits such as the input buffer connected to the pad are normally biased in the opposite voltage to that which the bond wire may be connected. For example, the input buffer circuitry connected to the bond pad, may see the pad as being connected to ground if the bond wires are connected, otherwise the input buffer circuitry will see the pad as being connected to VCC. When the pad is connected to a package pin then the end user may apply an electrical signal (e.g., supply voltage or ground) so that the integrated circuit may be configured as any one of a number of possible devices having one of a set of electrical attributes. Typically, the chip will have up to 8 such pads which can be used individually or in combination to configure the device. In one example, the chip would be part of an existing "family' of chips which all have, for example, N package pins. The extra package pins used to configure the chip would be added to one or both ends of the package so that the rest of the package looks like a normal non-configurable member of the "family'.
申请公布号 US2001043081(A1) 申请公布日期 2001.11.22
申请号 US19990326804 申请日期 1999.06.04
申请人 REES DAVID B. 发明人 REES DAVID B.
分类号 H03K19/173;(IPC1-7):H03K19/173 主分类号 H03K19/173
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