MPSoC performance estimation for cache variations

摘要

-38 MPSOC PERFORMANCE ESTIMATION FOR CACHE VARIATIONS Methods (400), apparatuses, and computer readable storage medium for determining performance of a multi-processor system having processors are described. Initial memory trace for the multi-processor system is generated (401). The initial memory trace has a sequence of time-ordered memory accesses originating from the processors for a first configuration of a shared cache. Generalised memory trace is generated (402) by replacing time-ordered memory accesses of initial memory trace with timing intervals to determine inter-processor memory access interference. Each timing interval is based on initial memory trace. Shared-cache statistics are calculated (403) for each timing interval based on the inter-processor memory access interference of the timing intervals for a second configuration of the shared-cache configuration. The performance of the system is determined (404) using the second configuration of the shared cache by updating timing intervals in generalised trace based on calculated shared-cache statistics and a dependency graph (301) of multi-processor system. The dependency graph (301)represents dependencies between processors. P132867 (9443744 1) -4/21 Generate initial memory trace Generate generalised memory trace Calculate caching statistics Determine performance Fig. 4