发明名称
摘要 An apparatus for sampling states of a computer system having a hierarchical memory arranged at a plurality of levels, the hierarchical memory storing data at addresses. The apparatus includes a selector for selecting memory transactions based on first state and transaction information. The memory transactions are to be processed by the hierarchical memory. A trigger activates the selector based on second state and transaction information. A sampler stores states of the computer system that are identified with the selected instructions while processing the selected memory transactions in the hierarchical memory. <IMAGE>
申请公布号 JP4371452(B2) 申请公布日期 2009.11.25
申请号 JP19980375361 申请日期 1998.11.26
申请人 发明人
分类号 G06F12/08;G06F11/34 主分类号 G06F12/08
代理机构 代理人
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