NON-VOLATILE MEMORY AND METHOD FOR REDUCED ERASE/WRITE CYCLING DURING TRIMMING OF INITIAL PROGRAMMING VOLTAGE

摘要

High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested in successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.