发明名称 |
Power-efficient interaction between multiple processors |
摘要 |
A technique for processing instructions in an electronic system is provided. In one embodiment, a processor of the electronic system may submit a unit of work to a queue accessible by a coprocessor, such as a graphics processing unit. The coprocessor may process work from the queue, and write a completion record into a memory accessible by the processor. The electronic system may be configured to switch between a polling mode and an interrupt mode based on progress made by the coprocessor in processing the work. In one embodiment, the processor may switch from an interrupt mode to a polling mode upon completion of a threshold amount of work by the coprocessor. Various additional methods, systems, and computer program products are also provided. |
申请公布号 |
US9529646(B2) |
申请公布日期 |
2016.12.27 |
申请号 |
US201313920320 |
申请日期 |
2013.06.18 |
申请人 |
Apple Inc. |
发明人 |
Hendry Ian;Sumpter Anthony G. |
分类号 |
G06F9/54;G06F9/38;G06F9/48;G06F9/50 |
主分类号 |
G06F9/54 |
代理机构 |
Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. |
代理人 |
Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C. |
主权项 |
1. A system, comprising:
a graphics processing unit (GPU); a central processing unit (CPU) configured to:
process an execution thread; andgenerate a plurality of work units related to the execution thread,wherein each work unit includes one or more associated processing tasks;write each of the work units to a buffer;assign one or more of the plurality of work units to the GPU;halt processing of the execution thread;enter an interrupt mode from a polling mode; and wherein the GPU is configured to:
access the one or more of the plurality of work units from the buffer;execute the one or more associated processing tasks included in each one of the one or more of the plurality of work units;write an indication of progress of executing the one or more associated processing tasks included in each of the one or more of the plurality of work units in a memory; andsend an interrupt signal to the CPU dependent upon completion of a subset of the one or more work units, wherein a particular work unit is complete when the one or more associated processing tasks included in the particular work unit have finished executing; wherein the CPU is further configured to:
repeatedly read the indication of progress from the memory; andestimate an amount of work remaining to be performed by the GPU based on the indication of progress;switch from the interrupt mode to the polling mode in response to a determination that the amount of work remaining is less than a threshold value, wherein the threshold value is dependent upon an operational mode of the CPU, and wherein the operational mode is one of at least a high performance mode or a low performance mode;while operating in the interrupt mode, resume processing of the execution thread in response to a determination that a first time period has elapsed or in response to receiving the interrupt signal; andwhile operating in the polling mode, resume processing of the execution thread in response to a determination that a second time period has elapsed or in response to receiving the interrupt signal, wherein the second time period is less than the first time period. |
地址 |
Cupertino CA US |