发明名称 |
Display apparatus drive circuit having plurality of cascade connnected drive ICs |
摘要 |
To prevent a timing shift of a clock and data supplied to a driver IC. A driver 1011 includes a phase adjustment circuit 201 for receiving via input terminals a clock and data outputted from a controller 103, latching received data with the clock adjusted to a 50-percent duty ratio, and outputting as phase-adjusted signals the data having the latched data further latched by synchronizing it with a delay clock having the duty-ratio-adjusted clock delayed by (pi/2) and the clock of the 50-percent duty ratio.
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申请公布号 |
US2004183794(A1) |
申请公布日期 |
2004.09.23 |
申请号 |
US20040766218 |
申请日期 |
2004.01.27 |
申请人 |
NEC ELECTRONICS CORPORATION |
发明人 |
AKAHORI HIDEKI |
分类号 |
G02F1/133;G09G3/20;G09G3/36;G09G5/00;(IPC1-7):G09G5/00 |
主分类号 |
G02F1/133 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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