发明名称 PROCESSOR DEBUG MECHANISM
摘要 <p>An overflow signal (OVF) of a counter (41) is used such that a time of overflow occurrence is a checkpoint, and the data at that time(for example, a signal (A), a control signal (V_A) and a counter value) are stored in a debug storing part (32). That is, for example, the control signal (V_A) and overflow signal (OVF) are inputted to an OR circuit (42), an output signal (a) of which is used to control the data storage and shift operation of the debug storing part (32). In this way, not only when the control signal (V_A) exhibits "1" but also at the time of overflow occurrence, the data (signal (A) and counter value at that time) are stored in the debug storing part (32).</p>
申请公布号 WO2007097039(A1) 申请公布日期 2007.08.30
申请号 WO2006JP303652 申请日期 2006.02.27
申请人 FUJITSU LIMITED;OHNUKI, YOSHITERU;YAMASHITA, HIDEO 发明人 OHNUKI, YOSHITERU;YAMASHITA, HIDEO
分类号 G06F11/22 主分类号 G06F11/22
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