发明名称 |
SPINTRONIC LOGIC ELEMENT |
摘要 |
An embodiment includes a C-element logic gate implemented as a spin logic device that provides a compact and low-power implementation of asynchronous logic by implementing a C-element with spintronic technology. An embodiment includes a first nanopillar including a first contact and a first fixed magnetic layer; a second nanopillar including a second contact and a second fixed magnetic layer; and a third nanopillar including a third contact, a tunnel barrier, and a third fixed magnetic layer; wherein (a) the first, second, and third nanopillars are all formed over a free magnetic layer, and (b) the third fixed magnetic layer, the tunnel barrier, and the free magnetic layer form a magnetic tunnel junction (MTJ). Other embodiments are described herein. |
申请公布号 |
US2016173100(A1) |
申请公布日期 |
2016.06.16 |
申请号 |
US201314906025 |
申请日期 |
2013.09.30 |
申请人 |
Intel Corporation |
发明人 |
NIKONOV DMITRI E.;MANIPATRUNI SASIKANTH;KISHINEVSKY MICHAEL;YOUNG IAN A. |
分类号 |
H03K19/16;H01L43/08;H01L27/22;H01L43/02 |
主分类号 |
H03K19/16 |
代理机构 |
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代理人 |
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主权项 |
1. A C-element comprising:
a first nanopillar including a first fixed magnetic layer and coupled to a first contact; a second nanopillar including a second fixed magnetic layer and coupled to a second contact; and a third nanopillar including a third fixed magnetic layer and coupled to a third contact; wherein (a) the first, second, and third nanopillars are all formed over a common free magnetic layer, and (b) the third fixed magnetic layer and the free magnetic layer form a magnetic tunnel junction (MTJ). |
地址 |
Santa Clara CA US |