HALF-POWER BUFFER AND/OR AMPLIFIER

摘要

Disclosed is a half-power buffer/amplifier. The half-power buffer/amplifier includes first and second amplifying blocks respectively corresponding to first and second channels, a first output buffer unit controlled by an output from the first amplifying block, and a second output buffer unit controlled by an output from the second amplifying block. Each of the first and second amplifying blocks includes an input unit configured to amplify a first input signal, thereby outputting first and second currents, and an amplifying unit including a first current mirror, a second current mirror, and a bias unit connected between the first current mirror and the second mirror. Nodes in the first and second amplifying blocks are selectively connected to source/drain terminals of transistors in the first and second amplifying blocks in response to a control signal.

主权项

1. A half-power buffer and/or amplifier comprising:
first and second amplifying blocks respectively corresponding to first and second channels; and a first output buffer unit controlled by an output from the first amplifying block and a second output buffer unit controlled by an output from the second amplifying block, wherein each of the first and second amplifying blocks comprises:
an input unit configured to amplify a first input signal, thereby outputting first and second currents, andan amplifying unit comprising a first current mirror comprising first and second transistors connected in series at a first node, configured to receive the first current, third and fourth transistors connected in series at a second node, configured to receive the first current or a complement thereof, a second current mirror comprising fifth and sixth transistors connected in series at a third node, configured to receive the second current, and seventh and eighth transistors connected in series at a fourth node, configured to receive the second current or a complement thereof, and a bias unit connected between the first current mirror and the second mirror, wherein the second and fourth nodes of the first and second amplifying blocks are selectively connected to first source/drain terminals of the fourth and eighth transistors in the first and second amplifying blocks in response to a control signal.