| 摘要 |
A chip packaging carrier (20), a chip and a PCB board, which relate to the field of microelectronics. A capacitor is mounted on the surface of the carrier for filtering, so that the electromagnetic radiation interference of the carrier is reduced, the integrity of a system signal is improved, the problem that a filtering effect is not good, caused due to the fact that the filtering capacitor is isolated due to a path ESL effect, is solved, thereby effectively utilizing a 3D space in a package and simplifying a circuit design on a product single board. The chip packaging carrier comprises: a top layer (201) for arranging a power supply network and communicating with a power supply pin of a capacitor or for arranging a ground wire and communicating with a ground pin of the capacitor, wherein the capacitor is arranged on the top layer; a second wiring layer (202) arranged below the top layer, wherein when the top layer is used for arranging the power supply network, the second wiring layer is used for arranging the ground wire and communicating with the ground pin of the capacitor, and when the top layer is used for arranging the ground wire, the second wiring layer is used for arranging the power supply network and communicating with the power supply pin of the capacitor; and a third wiring layer (203) arranged below the second wiring layer for arranging an IO lead wire. |
