发明名称 |
System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming process |
摘要 |
A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.
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申请公布号 |
US2004185623(A1) |
申请公布日期 |
2004.09.23 |
申请号 |
US20030392120 |
申请日期 |
2003.03.19 |
申请人 |
TAIWAN SEMICONDUCTOR MANAUFACTURING CO. |
发明人 |
SU HUNG-DER;WU SHIEN-YANG;CHEN YUNG-SHUN;SHIE TUNG-HENG;CHIU YUAN-HUNG |
分类号 |
H01L21/28;H01L21/3213;H01L21/8234;(IPC1-7):H01L21/338;H01L21/320;H01L21/476;H01L21/823 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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