| 摘要 |
A method for manufacturing a semiconductor device is provided to prevent an excessive oxidation of a lateral portion of a gate line and to restrain a self align fail of a landing plug contact by restraining the generation of an abnormal oxidation due to the difference of stress using a gate line etching process capable of removing a void generating point from a silicide layer. A gate line layer is formed on a semiconductor substrate. The gate line layer is composed of a first conductive layer, a second conductive layer and a hard mask. The second conductive layer is selectively etched by using the hard mask. A chemical etching process is performed on the resultant structure in order to obtain a negative etch cross-section from the second conductive layer. The first conductive layer is etched by using the hard mask as an etch barrier.
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