System and method for de-modulating a high-supply-domain differential signal and a common-mode clock in a front-end receiver

摘要

Techniques for de-modulating a high-supply-domain differential signal and a common-mode clock in a front-end receiver are described herein. In one embodiment, a method for receiving a signal comprises receiving the signal via a receiver input, the received signal comprising a differential signal and a common-mode clock signal. The method also comprises shifting the received signal from a first voltage range to a second voltage range that is lower than the first voltage range, and providing the shifted received signal on a first level-shifted signal line and a second level-shifted signal line. The method further comprises sensing voltage differences between the first and second level-shifted lines to recover the differential signal, and sensing common-mode voltages on the first and second level-shifted signal lines to recover the common-mode clock signal.

主权项

1. A receiver, comprising:
a receiver input with a first receive signal line and a second receive signal line for receiving a signal, the received signal comprising a differential signal and a common-mode clock signal; a voltage-level shifter coupled to the first and second receive signal lines, and configured to shift the received signal from a first voltage range to a second voltage range that is lower than the first voltage range, and to provide the shifted received signal on a first level-shifted signal line and a second level-shifted signal line; a data buffer having a differential input coupled to the first and second level-shifted signal lines, and configured to recover the differential signal by sensing voltage differences between the first and second level-shifted signal lines; and a clock recovery circuit coupled to the first and second level-shifted signal lines, and configured to recover the common-mode clock signal by sensing common-mode voltages on the first and second level-shifted signal lines.