发明名称 Time gain compensation
摘要 In certain embodiments, circuits and methods for time gain compensation are provided. A circuit includes a first op-amp that is configured to compare a first and a second input voltage signal received from first and second input circuits, respectively, and output a first op-amp output signal. A control circuit coupled with a first semiconductor element of the second input circuit is configured to vary a first resistance value of the first semiconductor element to control the first op-amp output signal. The first op-amp output signal includes a relatively high voltage signal and a relative low voltage signal when an input control voltage signal corresponds to a first reference voltage and a second reference voltage signal, respectively associated with the first op-amp. The first op-amp output signal is input to a gate terminal of a load semiconductor element so-as to vary an impedance of the load semiconductor element.
申请公布号 US8766721(B1) 申请公布日期 2014.07.01
申请号 US201213732151 申请日期 2012.12.31
申请人 Texas Instruments Incorporated 发明人 Dusad Shagun
分类号 H03F3/45 主分类号 H03F3/45
代理机构 代理人 Cooper Alan A. R.;Telecky, Jr. Frederick J.
主权项 1. A circuit for time gain compensation comprising: a first op-amp comprising an output terminal, the first op-amp configured to conduct a comparison between first and second input voltage signals and output a first op-amp output signal based on the comparison; a first input circuit coupled with the first op-amp and configured to provide the first input voltage signal to the first op-amp, the first input signal being generated based on signal levels of an input control voltage signal and a first reference voltage signal; a second input circuit comprising a first semiconductor element, the second input circuit coupled with the output terminal, the second input circuit configured to provide the second input voltage signal to the first op-amp, the second input voltage signal being generated based on signal levels of the first op-amp output signal and a relatively high voltage signal; and a control circuit coupled with the first semiconductor element and configured to vary a first resistance value of the first semiconductor element to thereby control the first op-amp output signal, the first op-amp output signal comprising the relatively high voltage signal when the input control voltage signal corresponds to the first reference voltage, and the first op-amp output signal comprising a relatively low voltage signal when the input control voltage signal corresponds to a second reference voltage signal, the relatively high voltage signal being higher than the relatively low voltage signal, the first op-amp output signal being input to a gate terminal of a load semiconductor element so as to vary an impedance of the load semiconductor element.
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