| 摘要 |
Y-word Search schemes under preferred hierarchical broken-GBL and broken-LBL NAND-CAM arrays with 1) one CSL line shared by two NAND blocks as a match line or 2) one LBLps line shared in each LG of H Blocks as a match line. The NAND-CAM includes three types of sense-amplifiers for Y-word search operations, including 1) an Analog SA with 3-Bias cascade circuit for LG-based LBLps match line, 2) a Digital-like SA circuit for Block-based CSL match line, and 3) an existing DR-SA along with decoders for Y-direction-CSL match line. One or more embodiments of the Y-word search operations are provided for finding one matched paired-block, then one matched block, and one matched Y-word string associated with a LBL using sequential On/Off technique without extra overhead. |
| 主权项 |
1. A method for performing Y-word search with variable length from a NAND-CAM array having divided groups with hierarchical 2-level bit lines and an independent power line in X direction as a match line per group, the method comprising:
providing a NAND-CAM array comprising J numbers of HG groups, each HG group being associated with N1 broken global bit lines (GBLs) laid at a first level along Y direction and being divided into L numbers of MG groups, each MG group being associated with N2 local bit lines (LBLs) laid at a second level below the first level in parallel to and respectively coupled to the N1 GBLs via a N2/N1-Y-pass circuit and being further divided into J′ numbers of LG groups, each LG group being associated with N2 broken-LBLs commonly pull down via a precharge circuit to one independent power line configured to be charged to a Vinh voltage, each broken-LBL forming a parasitic line capacitor serving as 1-bit dynamic cache register (DCR), each LG group including H numbers of blocks, each block including N2 numbers of strings respectively associated with the N2 broken-LBLs cascaded in a row along a word line (WL) or X direction orthogonal to the Y direction, each string comprising N3 numbers of NAND memory cells divided into two N3/2 numbers of complimentary sets of cells capped by a pair of string-select transistors respectively at two ends of the string having its source node connected to a common source line laid in the X direction shared by two neighboring blocks, wherein J, L, J′, H, N1, N2, and N3 are integers of 2 and greater based on memory chip density and design; providing multiple group-decoders including BHG-DEC, MG-DEC, BLG-DEC, and LG-based precharge power line decoder to generate respective gate control signals for dividing HG groups, coupling N1 broken-GBLs to N2 LBLs, dividing MG groups, and pulling down the broken-LBLs to the independent power line per LG group; providing a block-decoder with a latch circuit coupled to a voltage generator via a set of N3/2+1 pairs of complimentary bus lines in the Y direction and connected via corresponding block-gate transistors to a pseudo Y-page-buffer made by a corresponding set of N3/2 pairs of complimentary word lines plus two string-select gate lines in the X direction; setting the independent power line as a match line coupled to a LG-group based sense amplifier and a LG-group based ROM encoder circuit; loading a Y-word data, upon receiving a Y-word search command, to the pseudo Y-page-buffer associated with each block; determining the Y-word data having a length of a full block based on the Y-word search command, to set latch 2n number of complimentary voltages at each of N3/2 pairs of complimentary word lines plus two string-select gate lines, otherwise, to add necessary number of don't-care mask bits with a same highest value of the 2n number of complimentary voltages on remaining pairs of complimentary word lines to make the length of a full block, where n=1 for SLC Y-word search and n=2 for MLC Y-word search. |
