EFFICIENT CALIBRATION OF ERRORS IN MULTI-STAGE ANALOG-TO-DIGITAL CONVERTER

摘要

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

主权项

1. A multi-stage analog-to-digital converter with digitally assisted calibration, the multi-stage analog-to-digital converter comprising:
analog-to-digital converter stages in cascade, each analog-to-digital converter stage for generating a respective output code and a respective amplified output residue signal; wherein for each analog-to-digital converter stage, the multi-stage analog-to-digital converter further comprises:
a dedicated memory element for storing correction terms;a multiplexer selecting one of the correction terms in the dedicated memory element based on the respective output code; andcircuitry for correcting an error of the multi-stage analog-to-digital converter based on the selected correction term; and digital circuitry for computing the correction terms in the dedicated memory elements, wherein computing correction terms used for a given analog-to-digital converter stage takes into account an error term from one or more earlier analog-to-digital converter stages.