SYSTEMS AND METHODS FOR GENERATING INJECTION-LOCKED, FREQUENCY-MULTIPLIED OUTPUT SIGNALS

摘要

Disclosed herein are systems and methods for generating injection-locked, frequency-multiplied output signals. In an embodiment, a circuit includes a ring of a number (N) serially connected delay-buffer elements and an injection-pulse-generation circuit. Each delay-buffer element provides a time delay (D), and at least some of them have at least one pulse-locking injection port. The injection-pulse-generation circuit is configured to transmit balanced-delay injection-pulse signals—that are generated by applying balanced-delay selection logic to a clock signal according to pulse-selection control signals—to the pulse-locking injection ports to provide, at the ring output port, an injection-locked, frequency-multiplied output signal having a frequency that equals the reciprocal of (N*D) and that bears the same proportional relationship to the frequency of the clock signal that the period of the clock signal bears to (N*D).

主权项

1. A circuit system comprising a frequency-multiplication circuit, the frequency-multiplication circuit comprising:
a ring of a number (N) of serially connected delay-buffer elements that each provide an equal time delay (D), at least some of the delay-buffer elements having at least one pulse-locking injection port, the pulse-locking injection port being an edge driven pulse-locking injection port, the ring having a ring output port; and an injection-pulse-generation circuit comprising: a clock input port configured to receive a clock signal having a clock-signal frequency (FCLK) and a corresponding clock-signal period (TCLK); a pulse-selection input port configured to receive pulse-selection control signals; a plurality of injection-pulse output ports connected to respective pulse-locking injection ports of the delay-buffer elements; and balanced-delay selection-logic circuitry connected to the clock input port, the pulse-selection input port, and the injection-pulse output ports, wherein the injection-pulse generation circuit is configured to: generate balanced-delay injection-pulse signals by applying the balanced-delay selection-logic circuitry to the clock signal according to the pulse-selection control signals; and provide an injection-locked, frequency-multiplied ring output signal at the ring output port by transmitting the generated balanced-delay injection-pulse signals via the injection-pulse output ports to the respectively connected pulse-locking injection ports, the ring output signal having an output-signal frequency (FOUT) that equals the reciprocal of (N*D) and that bears the same proportional relationship to FCLK that TCLK bears to (N*D).