发明名称 ARITHMETIC PROCESSING DEVICE AND METHOD OF CONTROLLING ARITHMETIC PROCESSING DEVICE
摘要 An arithmetic processing device includes a plurality of arithmetic processing units each including, an internal circuit that, in an instruction processing state in which an instruction is processed, processes the instruction and that, in an instruction processing stopped state in which instruction processing is stopped, transitions to a state of power save operation, and a power control circuit that disables the power save operation; and a monitoring circuit that monitors the instruction processing stopped state of the plurality of arithmetic processing units and counts the number of the arithmetic processing units in the instruction processing stopped state. The power control circuit of each of the plurality of arithmetic processing units disables the power save operation of the arithmetic processing unit in the instruction processing stopped state, in a case where the number of the arithmetic processing units in the instruction processing stopped state exceeds a threshold.
申请公布号 US2016321070(A1) 申请公布日期 2016.11.03
申请号 US201615075274 申请日期 2016.03.21
申请人 FUJITSU LIMITED 发明人 Okazaki Ryohei;Gomyo Norihito
分类号 G06F9/30;G06F1/32 主分类号 G06F9/30
代理机构 代理人
主权项 1. An arithmetic processing device comprising: a plurality of arithmetic processing units each including, an internal circuit that, in an instruction processing state in which an instruction is processed, processes the instruction and that, in an instruction processing stopped state in which instruction processing is stopped, transitions to a state of power save operation; anda power control circuit that disables the power save operation; and a monitoring circuit that monitors the instruction processing stopped state of the plurality of arithmetic processing units and counts the number of the arithmetic processing units in the instruction processing stopped state, wherein the power control circuit of each of the plurality of arithmetic processing units disables the power save operation of the arithmetic processing unit in the instruction processing stopped state, in a case where the number of the arithmetic processing units in the instruction processing stopped state exceeds a threshold.
地址 Kawasaki-shi JP