| 摘要 |
The invention relates to a circuit arrangement (10) for simulating fault conditions in a line with two high-frequency capable signal lines, having two connectors (12a, b) for a first signal line and two connectors (14a, b) for a second signal line, wherein the two connectors (12a, b; 14a, b) are respectively connected by means of a line section (12, 14). An fault-circuit relay (24, 42) is arranged in each line section (12, 14) to provide a fault, wherein an output of each fault-circuit relay (24, 42) is connected to the line section (12, 14), and a further output is connected to a first fault-selection relay (26, 44), so that the outputs of the first fault-selection relays (26, 44) are each connected to second fault-selection relays (28, 40, 46). |
