发明名称 METHODS AND APPARATUS TO ELIMINATE PARTIAL-REDUNDANT VECTOR LOADS
摘要 Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector loads. An example apparatus includes a node group to associate a vector operation with a node group based on a load type of the vector operation. The example apparatus also includes a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group. The example apparatus also includes a code optimizer to determine replacement code based on a characteristic of the candidate, and to compare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.
申请公布号 US2016259628(A1) 申请公布日期 2016.09.08
申请号 US201514741160 申请日期 2015.06.16
申请人 Intel Corporation 发明人 Schuchman Farhana Aleen;Kreitzer David L.;Krishnaiyer Rakesh;Zakharin Vyacheslav Pavlovich;Preis Sergey;Borges Leonardo Jose;Thierry Philippe
分类号 G06F9/44;G06F11/36 主分类号 G06F9/44
代理机构 代理人
主权项 1. An apparatus to eliminate partial-redundant vector load operations, the apparatus comprising: a node group to associate a vector operation with a node group based on a load type of the vector operation; a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group; a code optimizer to: determine replacement code based on a characteristic of the candidate; andcompare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate; and a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.
地址 Santa Clara CA US