PROBELESS PARALLEL TEST SYSTEM AND METHOD FOR INTEGRATED CIRCUIT

摘要

A probeless parallel test system for an integrated circuit (IC) includes an IC chip, a wireless power receiving module and a Build-In Self-Test (BIST) circuit. The wireless power receiving module is electrically connected to the IC chip. The BIST circuit is electrically connected to the wireless power receiving module and the IC chip. The wireless power receiving module, the BIST circuit and the IC chip are all formed on a wafer. The wireless power receiving module is used to provide electric power to the BIST circuit and the IC chip. When receiving the electric power, the IC chip executes a functional operation, and transmits an operation result to the BIST circuit for testing.

主权项

1. A probeless parallel test system for an integrated circuit (IC), the probeless parallel test system comprising:
an IC chip; a wireless power receiving module electrically connected to the IC chip; and a Build-In Self-Test (BIST) circuit electrically connected to the wireless power receiving module and the IC chip; wherein the wireless power receiving module, the BIST circuit and the IC chip are all formed on as wafer, and the wireless power receiving module is used to provide electric power to the BIST circuit and the IC chip, and after receiving the electric power from the wireless power receiving module, the IC chip executes a functional operation, and transmits an operation result to the MST circuit for testing the correctness of the functional operation.