| 摘要 |
<p>First transistor rows (TR1) are arranged, each including two transistors (24a, 24b) connected in series for selectively connecting any of memory cell rows (MR) to an input/output circuit (16). A switching transistor (24a) operates as a switch and a short transistor(s) (24b) each having a source and a drain shorted to each other function(s) as wiring. The first transistor rows (TR1) are provided with a plurality of transistors (24a, 24b) in advance. Since there is no need to selectively form only such a transistor that is to be operated as a switch, there is no need to form ion-implanted regions for making a source and a drain per transistor. As a result, the spacing with which the transistors are arranged can be set without considering the layout rule of the diffusion layer regions. Since the transistors can be arranged closely, the layout area can be decreased and the chip size of the semiconductor memory can be reduced.</p> |
