发明名称 |
DELAY CIRCUIT, TESTING APPARATUS, TIMING GENERATOR, TEST MODULE AND ELECTRONIC DEVICE |
摘要 |
<p>A delay circuit for delaying an input signal and outputting the signal. The delay circuit is provided with a first delay element which receives the input signal, delays the input signal and outputs the signal; and a buffer which receives the delayed signal outputted from the first delay element, corrects delayed signal waveform deformation generated by the first delay element and outputs the signal. The delay circuit may be further provided with a second delay element which receives a delayed signal outputted from the buffer, delays the delayed signal and outputs the signal.</p> |
申请公布号 |
WO2006134837(A1) |
申请公布日期 |
2006.12.21 |
申请号 |
WO2006JP311606 |
申请日期 |
2006.06.09 |
申请人 |
ADVANTEST CORPORATION;SUDA, MASAKATSU;KANTAKE, SHUUSUKE |
发明人 |
SUDA, MASAKATSU;KANTAKE, SHUUSUKE |
分类号 |
H03K5/13;G01R31/28;G01R31/3183;H03K5/00 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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