Spare cell strategy using flip-flop cells

摘要

Configurable flip-flop cells for use in scan chain configurations include one or more multiplexers, a flip-flop, and one or more logic gates. The logic gates are configurable, through modification of different metallization or semiconductor layers, to operate as spare gates or to disable flip-flop cell outputs based selection signal switching between scan shift and capture mode. When disabling flip-flop cell outputs, the logic gates are configured to receive both a test signal and a data input signal and select one of the two to pass to the flip-flop based on the selection signal. When used as spare gates, the logic gates receive external inputs and provide spare gate outputs to circuitry on an integrated circuit that is external to the flip-flop cells.

主权项

1. An integrated circuit, comprising:
a first replicate flip-flop cell comprising:
a first multiplexer configured to receive a first data input, a first test input, and a selection signal and provide a first multiplexed output,a first flip-flop configured to generate a first internal data signal based on the first multiplexed output and a clock signal, anda first logic gate configured to generate a first flip-flop cell output in response to the first internal data signal and the selection signal, wherein said first flip-flop cell output is set to a fixed logic value if the selection signal is set to a first logic state and is permitted to change state in response to the first internal data signal if the selection signal is set to a second logic state; and a second replicate flip-flop cell comprising:
a second multiplexer configured to receive a second data input, a second test input, and the selection signal and provide a second multiplexed output,a second flip-flop configured to generate a second internal data signal based on the second multiplexed output and the clock signal, anda spare logic gate configured to receive one or more inputs from circuitry external to the second replicate flip-flop cell and generate a spare gate output in response to the one or more inputs from the circuitry external to the second replicate flip-flop cell.