MEMORY OPERATION LATENCY CONTROL

摘要

An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.

主权项

1. A method of operating an integrated circuit with memory, comprising:
performing a first operation on a memory array; and in response to a read command sequence after said first operation, performing a first read operation characterized by a first latency or performing a second read operation characterized by a second read latency, the first read operation being performed if a time delay between the first operation and the read command sequence is not less than a timing parameter, the second read operation being performed if said time delay is less than the timing parameter.