| 主权项 |
1. A vehicle electronic control apparatus in which a first CPU and a second CPU that are microprocessors provided in an engine control circuit unit and a transmission control circuit unit, respectively, collaborate with each other and in which the first CPU and the second CPU are mounted on a common circuit board and are contained in a common case or the first CPU and the second CPU are separately mounted on a first circuit board contained in a first case and on a second circuit board contained in a second case, respectively,
wherein a first monitoring control circuit unit including at least a first watchdog timer is connected with the first CPU; wherein the first CPU operates with opening/closing signals or analogue signals, as input signals, to be obtained from a first input-sensor group dedicated to engine control and a third input-sensor group utilized commonly in the engine control and transmission control, and generates at least a fuel injection control output for a fuel-injection electromagnetic valve and a valve-opening control output for an intake valve opening degree control motor for an intake valve provided in an intake throttle; wherein a valve-opening drive mechanism of the intake valve includes an initial-position returning mechanism that can perform saving operation based on a fixed intake valve opening degree when power supply to the intake valve opening degree control motor is stopped; wherein the operation of the second CPU is monitored by a runaway monitoring means included in a second monitoring control means or a second watchdog timer included in a second monitoring control circuit unit, and the runaway monitoring means is a means in which the first CPU monitors a watchdog signal to be generated by the second CPU; wherein a transmission to be controlled by the second CPU includes a transmission ratio fixation mechanism that makes it possible to travel at least forward at a fixed transmission ratio suitable for middle- or high-speed driving when the second CPU stops its operation; wherein the first watchdog timer measures the ON-time width and the OFF-time width of a first pulse train signal generated by the first CPU, and generates a first reset signal so as to initialize and restart the first CPU, when the pulse width becomes the same as or longer than the first threshold-value time; wherein the first monitoring control circuit unit is provided with a first control abnormality determination circuit including a communication abnormality determination circuit and a question-answer abnormality determination circuit, a mode selection first circuit, and a first gate circuit; wherein the first control abnormality determination circuit has a correct answer information data memory for transmission question data, sequentially transmits a plurality of question information pieces related to at least a valve-opening control output creation program to the first CPU in driving operation, receives from the first CPU answer information corresponding to the question information, and then compares the answer information with correct answer information preliminarily stored in the first monitoring control circuit unit, and the first control abnormality determination circuit determines whether or not a code check abnormality and an answering-response delay exist in the answer information so as to determine whether or not a first control abnormality including a communication abnormality and a question-answer abnormality exists and then to create a first control abnormality signal; wherein the mode selection first circuit has a first storage circuit that is set when a first state is established in which the occurrence count or the occurrence frequency of each of the first reset signal and the first control abnormality signal becomes the same as or larger than a predetermined threshold value, a first cutoff circuit that stops power supply to the intake valve opening degree control motor when the first storage circuit stores the occurrence of an abnormality, and a reset circuit that preliminarily initializes the first storage circuit when the power switch for starting power supply to the first CPU is closed; and wherein the first gate circuit resets the first CPU through the first reset signal and the first control abnormality signal when the first state has not been established, and after the first storage circuit has stored the occurrence of an abnormality, the first gate circuit prohibits the first control abnormality signal from performing reset processing of the first CPU so that a continuous non-runaway repeated abnormality related to valve-opening control is suppressed from providing an effect to fuel injection control. |
