<p>A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.</p>
申请公布号
WO2010011651(A1)
申请公布日期
2010.01.28
申请号
WO2009US51251
申请日期
2009.07.21
申请人
MICROCHIP TECHNOLOGY INCORPORATED;ZDENEK, JERROLD, S.;JULICHER, JOSEPH;DELPORT, VIVIEN;STEEDMAN, SEAN
发明人
ZDENEK, JERROLD, S.;JULICHER, JOSEPH;DELPORT, VIVIEN;STEEDMAN, SEAN