DEBUG CIRCUIT

摘要

A circuit for debugging timing of an LSI(Large Scale IC) logic circuit upon malfunction of an LSI mounted on a device substrate is provided to monitor multiple states in the LSI with small external pins by efficiently selecting a parallel signal in the logic circuit and converting it into a serial signal, as a selection circuit and a register rewritable from the outside of the LSI are installed. A selection block(120) selects/outputs a specified signal from multiple timing signals or multiple state signals output from the logic circuit(110). A timing generation block(130) selects a reference signal from multiple reference signals output from the logic circuit. A conversion block(140) outputs the serial signal by parallel converting the signal selected from the selection block into the serial signal with the timing of the reference signal output from the timing generation block. An output block(150) outputs the serial signal output from the conversion block to the outside.