| 摘要 |
The complexity of the logic of the cache coherency manager unit is reduced by leveraging the data path for intervention messages and responses to carry data associated with writeback requests. A processor core unit sends a writeback request to the cache coherency manager unit. The request does not include the writeback data. Upon receiving an intervention message associated with the writeback request, the processor core unit provides an intervention message response to the cache coherency manager unit indicating that the writeback operation should not be cancelled. The intervention message response includes the writeback data. Because the cache coherency manager already requires a data path to handle data transfers between processor core units, little or no additional overhead needs to be added to the cache coherency manager to handle data associated with writeback request.
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