发明名称 DISPLAY IN A GRAPHICAL FORMAT OF TEST RESULTS GENERATED USING SCENARIO MODELS
摘要 A method for testing a system-on-a-chip (SoC) is described. The method includes parsing a file to determine functions to be performed components of the SoC. The method further includes receiving a desired output of the SoC and generating a test scenario model based on the desired output of the SoC. The test scenario model includes a plurality of module representations of the functions and includes one or more connections between two of the module representations. The desired output acts as a performance constraint for the test scenario model. The test scenario model further includes an input of the SoC that is generated based on the desired output, the module representations, and the one or more connections. The test scenario model includes a path from the input via the module representations and the connections to the desired output.
申请公布号 US2016266203(A1) 申请公布日期 2016.09.15
申请号 US201615159576 申请日期 2016.05.19
申请人 Breker Verification Systems 发明人 Hamid Adnan;Qian Kairong;Do Kieu;Grosse Joerg
分类号 G01R31/3177;G06T11/20 主分类号 G01R31/3177
代理机构 代理人
主权项 1. A method comprising: generating a graphical display of multiple computer threads, wherein each computer thread includes one or more driver scenario models, wherein each driver scenario model includes a function associated with a test of one or more systems on chips (SoCs); and identifying a flow of execution of the driver scenario models from one of the computer threads to another one of the computer threads, wherein the flow of execution provides a sequence in which the one of the computer threads and the other one of the computer threads are executed.
地址 San Jose CA US