LOW TEMPERATURE POLYSILICON THIN FILM TRANSISTOR AND METHOD FOR FABRICATING SAME

摘要

The present invention provides a low temperature polysilicon thin film transistor and a fabricating method thereof. According to the method, a laser annealing process is performed to a remained portion of a a-Si layer on a substrate to form a first lightly doped drain (LDD) terminal, a second LDD terminal, a first phosphor material structure and a second phosphor material structure. A gate metal layer is then formed on the remained portion of the a-Si layer. A source metal layer and a drain metal layer are formed on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively. The present invention use the high temperature of the laser annealing process to perform a heat diffusion of phosphor material to form the LDD terminal and the phosphor material structure, the times of photomasks are used is reduced, and the process is simplified.

主权项

1. A method for fabricating a low temperature polysilicon thin film transistor, comprising:
depositing an N+ silicon doped layer on a substrate using a material comprising silane, phosphine and hydrogen, and forming a first doped layer and a second doped layer opposite to the first doped layer using a pattern etching process; depositing an amorphous silicon (a-Si) layer on the N+ silicon doped layer, performing a laser annealing process and a pattern etching process to the a-Si layer thereby remaining only a portion of the a-Si layer located in a channel between the first doped layer and the second doped layer, wherein the a-Si layer is recrystallized into a polysilicon thin film by the laser in the lase annealing process, a high temperature effect applied to the remained portion of the a-Si layer by the laser annealing forming a first lightly doped drain (LDD) terminal between the first doped layer and the remained portion of the a-Si layer, and form a second LDD terminal between the second doped layer and the remained portion of the a-Si layer, form a first phosphor material structure on the first doped layer and the first LDD terminal, and form a second phosphor material structure on the second doped layer and the second LDD terminal, wherein the first LDD terminal and the first phosphor material structure are formed by a high temperature diffusion process of phosphor material contained in the first doped layer, and the second LDD terminal and the second phosphor material structure are formed by a high temperature diffusion process of phosphor material contained in the second doped layer; forming a gate metal layer on the remained portion of the a-Si layer, and forming a source metal layer and a drain metal layer on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively.