摘要 |
A data processor comprising: a register memory comprising an array of memory cells and a processing unit that executes instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret one form of second instruction part as specifying a first group of cells 130 together with a second group of cells 132, wherein none of the cells of the first group of cells 130 adjoins any of the cells of the second group 132. This is useful in video data processing and compression. |