发明名称 |
Combination field programmable gate array allowing dynamic reprogrammability |
摘要 |
A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.
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申请公布号 |
US2005169040(A1) |
申请公布日期 |
2005.08.04 |
申请号 |
US20040857667 |
申请日期 |
2004.05.28 |
申请人 |
PENG JACK Z.;LIU ZHONGSHANG;FONG DAVID;YE FEI |
发明人 |
PENG JACK Z.;LIU ZHONGSHANG;FONG DAVID;YE FEI |
分类号 |
H01L21/822;G11C11/24;G11C11/34;G11C11/401;G11C11/405;G11C11/406;G11C16/02;G11C17/16;H01L21/82;H01L21/8242;H01L27/02;H01L27/04;H01L27/108;H01L27/118;H03K17/687;H03K19/173;H03K19/177;(IPC1-7):G11C11/34 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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