Mismatch and noise insensitive sense amplifier circuit for STT MRAM

摘要

A technique for sensing a data state of a data cell. A comparator has a first input at a node A and a second input at a node B. A first n-channel transistor is connected to a first p-channel transistor at the node A. A second n-channel transistor is connected to a second p-channel transistor at the node B. A multiplexer is configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second n-channel transistor. The comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.

主权项

1. A system for sensing a data state of a data cell, the system comprising:
a comparator having a first input at a node A and a second input at a node B; a first n-channel transistor connected to a first p-channel transistor at the node A; a second n-channel transistor connected to a second p-channel transistor at the node B; a first switch connected to a gate and a drain of the first p-channel transistor, wherein the first switch is configured to selectively connect the drain of the first p-channel transistor to a voltage supply via a first capacitor; a second switch connected to a gate and a drain of the second p-channel transistor, wherein the second switch is configured to selectively connect the drain of the second p-channel transistor to the voltage supply via a second capacitor; and a multiplexer configured to selectively connect a first reference cell or the data cell to the first n-channel transistor and configured to selectively connect the data cell or a second reference cell to the second n-channel transistor; wherein the comparator outputs the data state of the data cell based on input of a node A voltage at the node A and a node B voltage at the node B.