VERTICAL GATE ALL-AROUND TRANSISTOR

摘要

Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.

主权项

1. A vertical field effect transistor, comprising:
a silicon substrate having a front surface and a back surface; an epitaxial source region; an epitaxial drain region; a channel located between the source region and the drain region, the channel having a channel axis that is oriented transverse to the front surface of the substrate; a gate that wraps around the channel, the gate configured to control current flow in the channel; a low-k encapsulant, overlying and in contact with the gate; and one or more electrical contacts accessible from the back surface of the substrate.