发明名称 |
SYSTEMS AND METHODS FOR SRAM WITH BACKUP NON-VOLATILE MEMORY THAT INCLUDES MTJ RESISTIVE ELEMENTS |
摘要 |
A memory device has an SRAM that stores a logic state. A first MTJ has two terminals. A second one of the terminals is coupled to a storing node. A first terminal of a second MTJ is coupled to the storing node. The first and second MTJs are programmed to a first resistance by flowing current from the first second terminals and to a second resistance by flowing current from the second to first terminal. A storing circuit is coupled to the storing node, the SRAM cell, and a non-volatile word line. The storing circuit couples the logic state of the SRAM cell to the storing node during a store mode. The logic state of the SRAM cell is stored in the first and second MTJs by applying a storing voltage between the first terminal of the first MTJ and the second terminal of the second MTJ of a first polarity then a second polarity. |
申请公布号 |
US2016343436(A1) |
申请公布日期 |
2016.11.24 |
申请号 |
US201514716729 |
申请日期 |
2015.05.19 |
申请人 |
FREESCALE SEMICONDUCTOR, INC. |
发明人 |
ROY ANIRBAN;SADD MICHAEL A. |
分类号 |
G11C14/00;G11C11/419 |
主分类号 |
G11C14/00 |
代理机构 |
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代理人 |
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主权项 |
1. A memory device, comprising:
an SRAM cell that stores a logic state; a first MTJ having a first terminal and a second terminal coupled to a storing node; a second MTJ having a first terminal and a second terminal, wherein the first terminal of the second MTJ is coupled to the storing node, and wherein the first and second MTJs are characterized as being programmed to a first resistance state by flowing current from the first terminal to the second terminal and to a second resistance state, different from the first resistance state, by flowing current from the second terminal to the first terminal; a storing circuit coupled to the storing node, the SRAM cell, and a non-volatile word line, wherein the storing circuit couples the logic state of the SRAM cell to the storing node during a store mode; wherein, during the store mode, the logic state of the SRAM cell is stored in the first and second MTJs by applying a storing voltage between the first terminal of the first MTJ and the second terminal of the second MTJ of a first polarity during a first time period of a store operation and a second polarity during a second time period of the store operation. |
地址 |
Austin TX US |