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1. A GOA circuit of LTPS semiconductor TFT, employed for forward-backward bidirectional scan transmission, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors and comprises a transmission part, a transmission control part, an information storage part, a data erase part, an output control part and an output buffer part;
the transmission part is electrically coupled to a first low frequency signal, a second low frequency signal, a driving output end of an N−1th GOA unit which is the former stage of the Nth GOA unit, a driving output end of an N+1th GOA unit which is the latter stage of the Nth GOA unit and the information storage part; the transmission control part is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, an M−2th sequence signal, a high voltage source, a low voltage source and the information storage part; the information storage part is electrically coupled to the transmission part, the transmission control part, the data erase part, the high voltage source and the low voltage source; the data erase part is electrically coupled to the information storage part, the output control part, the high voltage source and the reset signal end; the output control part is electrically coupled to the data erase part, the output buffer part, a driving output end, a sequence signal, the high voltage source and the low voltage source; the output buffer part is electrically coupled to the output control part, an output end, the high voltage source and the low voltage source; voltage levels of the first low frequency signal and the second low frequency signal are switched along with the forward-backward scan, and the first low frequency signal is equivalent to a direct current high voltage level, and the second low frequency signal is equivalent to a direct current low voltage level as forward scan; the first low frequency signal is equivalent to a direct current low voltage level, and the second low frequency signal is equivalent to a direct current high voltage level as backward scan; the transmission part comprises a first P-type transistor, and a gate of the first P-type transistor is electrically coupled to the second low frequency signal, and a source is electrically coupled to the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to a first node; a second N-type transistor, and a gate of the second N-type transistor is electrically coupled to the first low frequency signal, and a source is electrically coupled to the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to the first node; a third P-type transistor, and a gate of the third P-type transistor is electrically coupled to the first low frequency signal, and a source is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and a drain is electrically coupled to a second node; a fourth N-type transistor, and a gate of the fourth N-type transistor is electrically coupled to the second low frequency signal, and a source is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and a drain is electrically coupled to the second node; the transmission control part comprises: a fifth P-type transistor, and a gate of the fifth P-type transistor is electrically coupled to the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, and the source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a sixth P-type transistor; the sixth P-type transistor, and a gate of the sixth P-type transistor is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and a source is electrically coupled to the drain of the fifth P-type transistor, and a drain is electrically coupled to a source of a seventh N-type transistor; the seventh N-type transistor, and a gate of the seventh N-type transistor is electrically coupled to the driving output end of the N−1th GOA unit which is the former stage of the Nth GOA unit, and a source is electrically coupled to the drain of the sixth P-type transistor, and a drain is electrically coupled to the low voltage source; an eighth N-type transistor, and the gate of the eighth N-type transistor is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and the source is electrically coupled to the drain of the sixth P-type transistor, and a drain is electrically coupled to the low voltage source; a ninth P-type transistor, and a gate of the ninth P-type transistor is electrically coupled to the drain of the sixth P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a tenth N-type transistor; the tenth N-type transistor, and a gate of the tenth N-type transistor is electrically coupled to the drain of the sixth P-type transistor, and the source is electrically coupled to the drain of the ninth P-type transistor, and a drain is electrically coupled to the low voltage source; an eleventh P-type transistor, a gate of the eleventh P-type transistor is electrically coupled to the drain of the sixth P-type transistor, and a source is electrically coupled to a source of a twelfth N-type transistor, and a drain is electrically coupled to the M−2th sequence signal; the twelfth N-type transistor, and a gate of the twelfth N-type transistor is electrically coupled to the drain of the ninth P-type transistor, and the source is electrically coupled to the source of the eleventh P-type transistor, and a drain is electrically coupled to the M−2th sequence signal; the information storage part comprises: a thirteenth N-type transistor, and a gate of the thirteenth N-type transistor is electrically coupled to the source of the eleventh P-type transistor, and a source is electrically coupled to a drain of a fourteenth P-type transistor, and a drain is electrically coupled to the low voltage source; the fourteenth P-type transistor, and a gate of the fourteenth P-type transistor is electrically coupled to the source of the eleventh P-type transistor, and a source is electrically coupled to the high voltage source, and the drain is electrically coupled to the source of the thirteenth N-type transistor; a fifteenth P-type transistor, and a gate of the fifteenth P-type transistor is electrically coupled to the source of the thirteenth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a sixteenth P-type transistor; the sixteenth P-type transistor, and a gate of the sixteenth P-type transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the fifteenth P-type transistor, and a drain is electrically coupled to a source of a seventeenth N-type transistor; the seventeenth N-type transistor, and a gate of the sixteenth P-type transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the sixteenth P-type transistor, and a drain is electrically coupled to a source of an eighteenth N-type transistor; the eighteenth N-type transistor, and a gate of the eighteenth N-type transistor is electrically coupled to the source of the eleventh P-type transistor, and the source is electrically coupled to the drain of the seventeenth N-type transistor, and a drain is electrically coupled to the low voltage source; a nineteenth P-type transistor, and a gate of the nineteenth P-type transistor is electrically coupled to the gate of the thirteenth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a twentieth P-type transistor; the twentieth P-type transistor, and a gate of the twentieth P-type transistor is electrically coupled to the second node, and the source is electrically coupled to the drain of the nineteenth P-type transistor, and a drain is electrically coupled to a source of a twenty-first N-type transistor; the twenty-first N-type transistor, and a gate of the twenty-first N-type transistor is electrically coupled to the second node, and the source is electrically coupled to the drain of the twentieth P-type transistor, and a drain is electrically coupled to a source of a twenty-second N-type transistor; the twenty-second N-type transistor, and a gate of the twenty-second N-type transistor is electrically coupled to the source of the thirteenth N-type transistor, and the source is electrically coupled to the drain of the twenty-first N-type transistor, and a drain is electrically coupled to the low voltage source; the data erase part comprises: a twenty-third P-type transistor, and a gate of the twenty-third P-type transistor is electrically coupled to the reset signal end, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the drain of the sixteenth P-type transistor and the drain of the twentieth P-type transistor; the output control part comprises: a twenty-fourth P-type transistor, and a gate of the twenty-fourth P-type transistor is electrically coupled to the drain of the sixteenth P-type transistor and the drain of the twentieth P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the driving output end; a twenty-fifth N-type transistor, and a gate of the twenty-fifth N-type transistor is electrically coupled to the drain of the sixteenth P-type transistor and the drain of the twentieth P-type transistor, and a source is electrically coupled to the driving output end, and a drain is electrically coupled to the low voltage source; a twenty-sixth P-type transistor, and a gate of the twenty-sixth P-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a twenty-ninth N-type transistor; a twenty-seventh N-type transistor, and a gate of the twenty-seventh N-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to a drain of the twenty-ninth N-type transistor, and a drain is electrically coupled to the low voltage source; a twenty-eighth P-type transistor, and a gate of the sixteenth P-type transistor is electrically coupled to the sequence signal, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the source of the twenty-ninth N-type transistor; the twenty-ninth N-type transistor, and a gate of the twenty-ninth N-type transistor is electrically coupled to the sequence signal, and the source is electrically coupled to the drain of twenty-sixth P-type transistor, and a drain is electrically coupled to the source of the twenty-seventh N-type transistor; the output buffer part comprises: a thirtieth P-type transistor, and a gate of the thirtieth P-type transistor is electrically coupled to the source of the twenty-ninth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a thirty-first N-type transistor; the thirty-first N-type transistor, and a gate of the thirty-first N-type transistor is electrically coupled to the source of the twenty-ninth N-type transistor, and the source is electrically coupled to the drain of the thirtieth P-type transistor, and a drain is electrically coupled to the low voltage source; a thirty-second P-type transistor, and a gate of the thirty-second P-type transistor is electrically coupled to the drain of the thirtieth P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a thirty-third N-type transistor; the thirty-third N-type transistor, and a gate of the thirty-third N-type transistor is electrically coupled to the drain of the thirtieth P-type transistor, and the source is electrically coupled to the drain of the thirty-second P-type transistor, and a drain is electrically coupled to the low voltage source; a thirty-fourth P-type transistor, and a gate of the thirty-fourth P-type transistor is electrically coupled to the drain of the thirty-second P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the output end; a thirty-fifth N-type transistor, and a gate of the thirty-fifth N-type transistor is electrically coupled to the drain of the thirty-second P-type transistor, and a source is electrically coupled to the output end, and a drain is electrically coupled to the low voltage source. |
