| 摘要 |
A data transfer device, a clock switching circuit, and a clock switching method are provided to decrease a jitter by suppressing a phase difference between parallel clock signals. A first S/P(Series/Parallel) converter(10) converts a first serial signal of a first system to a first parallel signal and restores a first clock of the first system from the first serial signal. A second S/P converter(20) converts a second serial signal of a second system to a second parallel signal and restores a second clock of the second system from the second serial signal. A data switching unit(46) selects one of the first and second parallel signals as a select parallel signal according to a switch control signal indicating a selected system. A clock switching unit(50) selects one of the first and second clocks as a select clock according to a switch control signal. A P/S(Parallel/Series) converter(30) converts the selected parallel signal to a serial output signal by using the select clock. A phase comparator outputs a phase difference between one of the non-selected clocks and the select clock. A phase shifter(52) shifts a phase of the select clock according to the phase difference at a system change timing, when the selected system indicated by the switch control signal is changed.
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