发明名称 Method for controlling non-volatile semiconductor memory system
摘要 In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.
申请公布号 US8756401(B2) 申请公布日期 2014.06.17
申请号 US200410913865 申请日期 2004.08.06
申请人 Kabushiki Kaisha Toshiba 发明人 Tanaka Yoshiyuki;Yatabe Makoto;Sato Takeaki;Kawamoto Kazuya
分类号 G06F12/10 主分类号 G06F12/10
代理机构 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. 代理人 Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
主权项 1. A method for controlling a non-volatile semiconductor memory system including a non-volatile semiconductor memory having a first group of physical blocks and a second group of physical blocks, comprising: writing a first address translation table by entering a plurality of entries for a first zone on a random access memory in the non-volatile semiconductor memory system, the first address translation table indicating a relationship between a first group of logical blocks and the first group of physical blocks; checking whether a logical block address corresponds to the first zone, the logical block address being received from a host system requesting an access to the non-volatile semiconductor memory system; and if the logical block address does not correspond to the first zone, writing a second address translation table by entering a plurality of entries for a second zone on the random access memory, the second address translation table indicating a relationship between a second group of logical blocks and the second group of physical blocks, wherein the second group of physical blocks does not overlap with the first group of physical blocks, wherein when the second address translation table is written on the random access memory, at least one part of the first address translation table is deleted from the random access memory.
地址 Kawasaki-shi JP
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