发明名称 LAYOUT DESIGN METHOD USING SOFT MACRO, DATA STRUCTURE FOR SOFT MACRO AND CREATION METHOD FOR SOFT MACRO LIBRARY
摘要 PROBLEM TO BE SOLVED: To suppress the increase of the area of a chip, and to reduce the number of times of repeated layout and design man-hours for timing convergence in chip layout. SOLUTION: A soft macro (14) includes: relative arrangement position determined cell information (31) indicating a plurality of relative arrangement position determined cells (43), (44) whose relative positions are determined; relative position information (32) indicating the relative position; and pieces of arrangement position determined wiring information (33), (34) indicating wiring (45) whose arrangement positions are determined in accordance with the plurality of relative position determined cells (43), (44). Then, the soft macro (14) does not change the layout of the relative position determined cells (43) and (44) and the wiring (45), when determining the arrangement position and wiring in an IC chip on the basis of a net list (11). COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009134439(A) 申请公布日期 2009.06.18
申请号 JP20070308994 申请日期 2007.11.29
申请人 NEC ELECTRONICS CORP 发明人 ANDO TETSUO
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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