发明名称 |
Dual damascene process using high selectivity boundary layers |
摘要 |
A method of manufacturing a semiconductor device with multiple dual damascene structures that maintains the maximum density. A first dual damascene structure having a first via and a first trench is formed in a first interlayer dielectric and a first etch stop layer formed on the planarized surface of the first interlayer dielectric. Two layers of interlayer dielectric separated by a second etch stop layer is formed on the surface of the first etch stop layer. A third etch stop layer is formed on the upper layer of interlayer dielectric and a first photoresist layer formed on the third etch stop layer. The photoresist layer is etched having a dimension coinciding with a width dimension of the first via. The third etch stop layer is selectively etched and the first photoresist layer removed and replaced by a second photoresist layer. The second photoresist layer is etched having a dimension coinciding with a width dimension of the first trench. The two layers of interlayer dielectric and the first, second and third etch stop layers are etched to form a second dual damascene structure having a second via and a second trench having the same dimensions as the first dual damascene structure.
|
申请公布号 |
US6025259(A) |
申请公布日期 |
2000.02.15 |
申请号 |
US19980109113 |
申请日期 |
1998.07.02 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
YU, ALLEN S.;STEFFAN, PAUL J.;SCHOLER, THOMAS CHARLES |
分类号 |
H01L21/768;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/768 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|