| 摘要 |
PURPOSE: A timing signal generating circuit and a semiconductor IC(Integrated Circuit) device are provided to permits timing design with relatively high adjustment accuracy to be done in a short period and to realize a signal transmission system capable of high-speed, error-free signal transmission without being affected by skew on each signal line. CONSTITUTION: In the device, a timing buffer circuit(271) includes a flip-flop(30) which is constructed using inverters(31,32) with the output of each inverter connected to the input of the other. The input end of the flip-flop(30) is connected to the drains of pMOS transistors(33A,33B) and an nMOS transistor(35); the sources of the pMOS transistors(33A) and(33B) are connected to power supply line VDD, while the source of the nMOS transistor(35) is connected to ground line. The output of the flip-flop(30) is supplied to one input of an AND gate(36) whose other input is supplied with the control command CNTC.
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