发明名称 DATA PROCESSOR
摘要 PROBLEM TO BE SOLVED: To secure high reliability in order to set the order of processing based on event signals which simultaneously occur from one circuit module to the order of priority by clarifying that those event signals are related to simultaneous occurrence even when the event signals related to the simultaneous occurrence are subsequently accepted due to wiring delay or crosstalk delay.SOLUTION: A simultaneous occurrence flag to be set (changed from a first state to a second state) when a plurality of event signals simultaneously occur from one circuit which synchronously operates is prepared. When it is determined that the event signals related to the simultaneous occurrence have occurred by referring to the simultaneous occurrence flag, processing corresponding to the event signals related to the simultaneous occurrence is executed in the order of priority, or a request for instructing or starting the processing is issued in the order of priority.
申请公布号 JP2014137606(A) 申请公布日期 2014.07.28
申请号 JP20130004290 申请日期 2013.01.15
申请人 RENESAS ELECTRONICS CORP 发明人 NAKAJIMA KENICHI
分类号 G06F9/48;G06F15/78 主分类号 G06F9/48
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