| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain an output buffer circuit with a high slew rate wherein slew rate variations are reduced. <P>SOLUTION: An NMOS transistor M3 of the output buffer circuit is turned on to decrease a gate voltage of a PMOS transistor M1 being an output transistor to a threshold voltage or below by a capacitance ratio of a capacitor C1 and a capacitor C2 and to turn on the PMOS transistor M1. Simultaneously, a current source I1 finally brings the gate voltage of the PMOS transistor M1 to a zero voltage and turns on a PMOS transistor M4 to decrease a gate voltage of an NMOS transistor M2 being an output transistor to a threshold voltage or below by a capacitance ratio of a capacitor C3 and a capacitor C4 and to turn on the NMOS transistor M2. Simultaneously, a current source I2 finally brings the gate voltage of the NMOS transistor M2 to a power supply voltage level as its configuration, and the gate voltage of the output transistors is controlled by capacitance division. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
