| 摘要 |
A high performance instruction cache method for facilitating operation of a processor core coupled to a first memory containing executable instructions, and a second memory with a faster speed than the first memory is provided. The method includes examining instructions from the first memory filled into the second memory and extracting instruction information containing at least branch information. The method also includes creating a plurality of tracks based on the extracted instruction information. Further, the method includes filling at least one or more instructions that are possibly executed by the processor core from the first memory into the second memory based on one or more tracks from a plurality of instruction tracks. |
