EFFICIENCY OF AN INSTRUCTION CACHE BY RETRIEVING INSTRUCTIONS FOR COMPLETING A SINGLE BRANCH BACKWARDS SHORT LOOP FROM A LOCAL LOOP BUFFER

摘要

A method and system for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycles of the single branch, backwards short loop, rather than from the instruction cache.

主权项

1. A processor comprising:
one or more execution units; an instruction cache having instructions stored therein for execution by the one or more execution units; and an instruction unit circuit coupled to the one or more execution units and which provides instructions fetched from the instruction cache to the one or more execution units for execution, wherein the instruction unit circuit comprises a plurality of physical instruction buffers, and wherein the instruction unit circuit is configured to:
detect a presence of a single branch, backwards short loop within a stream of fetched instructions;add a plurality of virtual loop buffer subdivisions to each of the plurality of physical instruction buffers;create a virtual loop buffer that is physically distributed substantially equally across the plurality of virtual loop buffer subdivisions;determine whether the number of instructions in the single branch, backwards short loop is greater than the capacity of the virtual loop buffer; andin response to determining that the number of instructions in the single branch, backwards short loop is not greater than the capacity of the virtual loop buffer, temporarily buffer the single branch, backwards short loop in the virtual loop buffer, wherein the instructions of the single branch, backwards short loop are distributed substantially equally across each virtual loop buffer subdivision based on the number of instructions in the single branch, backwards short loop.