Processor with granular add immediates capability and methods

摘要

A processor can address a double-word sized memory space (e.g., 64 bit addressing). The processor can be configured to decode a series of three instructions that cause 48 bits of an arbitrary 64 bit immediate value to be constructed in a register and a fourth instruction that completes the 64-bit value and branches to or accesses a memory location determined used the 64-bit value in the register. A separate instruction in an instruction set architecture can be provided for non-destructive writing of 16-bit portions of a 64 bit register.