| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a DLL (Delay Locked Loop) circuit capable of preventing data from being erroneously latched affected by jitter when generating a signal synchronized with a reference clock signal. <P>SOLUTION: The DLL circuit comprises: a delay circuit 12 for outputting signals D1, D2 delaying a reference clock signal CLK according to control signals C1, C2; an interpolation circuit 13 for interpolating a phase difference between the signals D1, D2; an output circuit 14, 15 for outputting DQ/DQS signals with internal clock signals CLK0 as timing references; a dummy output circuit 16 which inputs the internal clock signal CLK0 and outputs a feedback clock signal RCLK of the same phase as that of the DQ/DQS signal; a phase comparator circuit 17 for comparing phases of the reference clock signal CLK and the feedback clock signal RCLK; and first and second delay control circuits 18, 19 each for controlling the increase/decrease of the control signal C1, C2 in a phase matching direction, wherein the signal D2 is controlled to enlarge a delay time only for one cycle of the reference clock signal CLK in comparison with the signal D1. <P>COPYRIGHT: (C)2007,JPO&INPIT |
