| 摘要 |
PROBLEM TO BE SOLVED: To decrease a contact resistance and a carrier implantation efficiency. SOLUTION: A p-type impurity layer 2 is formed in an n-type semiconductor substrate 1. An impurity concentration of the p-type impurity layer 2 is low and further the depth is 1.0μm or less, sufficiently shallow, so that the carrier implantation efficiency is decreased. A heavily doped p-type contact layer 4 is formed in the p-type impurity layer 2 so as to decrease a contact resistance. As the depth of a p-type contact layer 4 is 0.2μm or less, sufficiently shallow, it does not affect the carrier implantation efficiency. Furthermore, a silicide layer 5 is formed between the p-type contact layer 4 and an electrode 3 so as to reach a peak position of a concentration profile of the p-type contact layer. This silicide layer 5 may realize a further reduction in the contact resistance.
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