发明名称 RECONFIGURABLE LOGIC DEVICE
摘要 A reconfigurable logic device includes logic units and allows logic circuits to be formed according to configuration data. The logic units each include a configuration memory that stores first and second configuration data, a first address input line through which a clock is inputted as a first address for the configuration memory, a second address input line through which an input of a data input line is inputted as a second address for the configuration memory, a register unit that, according to the clock, reads the second configuration data specified by the first address from the configuration memory and retains the second configuration data, and outputs the first configuration data in a previous state, and a multiplexer that, according to the first or second configuration data outputted from the register unit, selectively combines a data input from the data input line and a data output to a data output line.
申请公布号 US2016241245(A1) 申请公布日期 2016.08.18
申请号 US201615046777 申请日期 2016.03.08
申请人 Taiyo Yuden Co., Ltd. 发明人 SATOU Masayuki;SHIMIZU Isao
分类号 H03K19/177 主分类号 H03K19/177
代理机构 代理人
主权项 1. A reconfigurable logic device comprising a plurality of logic units and configured to allow a plurality of logic circuits to be formed in accordance with configuration data, wherein each of the logic units includes a configuration memory configured to store first configuration data and second configuration data,a data input line,a data output line,a first address input line through which a clock is inputted as a first address for the configuration memory,a second address input line through which an input of the data input line is inputted as a second address for the configuration memory,a register unit configured to, in accordance with the clock, read the second configuration data specified by the first address from the configuration memory and retain the second configuration data, and output the first configuration data retained in a previous state, anda reconfigurable logic multiplexer configured to, in accordance with the first configuration data or the second configuration data outputted from the register unit, selectively combine a data input from the data input line and a data output to the data output line, and/or output, to the data output line, data produced by a logical operation related to a data input from the data input line, and wherein adjacent ones of the logic units are connected by the data input line and the data output line.
地址 Tokyo JP